2009 · 63 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingLow-power Digital Circuit DesignAnalog-to-digital Converter DesignCmos Digital Circuit DesignCmos ScalingEnergy-efficient Digital CircuitsPower ConsumptionPower Consumption Optimization
A novel 2-dimension Vernier Time to digital converter (TDC) is presented. The proposed architecture reduces drastically the number of delay stage required by linear TDCs minimizing the power consumption and the area of the design. A 7 bits TDC prototype realized in 65 nm CMOS technology is presented. The chip has a resolution of 4.8 ps with a power consumption of 1.7 mW at a conversion rate of 50 Msps.
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