Time to digital converter based on a 2-dimensions Vernier architecture

Abstract

A novel 2-dimension Vernier Time to digital converter (TDC) is presented. The proposed architecture reduces drastically the number of delay stage required by linear TDCs minimizing the power consumption and the area of the design. A 7 bits TDC prototype realized in 65 nm CMOS technology is presented. The chip has a resolution of 4.8 ps with a power consumption of 1.7 mW at a conversion rate of 50 Msps.