The Second Stage of a Thin Wafer IGBT Low Loss 1200V LPT-CSTBT™ with a Backside Doping Optimization Process

Abstract

We have done research for the purpose of improving of total performance of 1200V light punch-through (LPT) IGBTs that utilizing carrier stored trench-gate bipolar transistor (CSTBTtrade). This paper reports that the total loss can be dramatically improved by a vertical shrink of LPT-CSTBT to a structure with a thin N drift and a new backside collector layer possessed of both reinforced N buffer and lengthened carrier lifetime. The new LPT-CSTBT demonstrates lower on-state voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE(sat)</sub> ), lower turn-off loss (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF </sub> ), lower junction leakage current (@398 ~ 423K) than that of the conventional one presented in ISPSD'02. Our results show, for the first time, that the proposed new collector structure is much more effective as a collector one because of making it positive to choose any position in the trade-off characteristic between V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE(sat)</sub> and E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> without utilizing any conventional carrier lifetime technique. From the viewpoint of low total loss and choosing widely characteristic position in the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE(sat)</sub> and E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> trade-off curve, the new LPT-CSTBT with new LPT technology is a promising candidate for high voltage power device