An economical class of digital filters for decimation and interpolation

TLDR

The paper presents a class of digital linear‑phase FIR filters for decimation and interpolation. These filters are built from cascaded ideal integrator stages at a high sampling rate and an equal number of comb stages at a low sampling rate, with the number of pairs chosen to meet aliasing or imaging specifications, and design procedures and examples are provided. The resulting filters need no multipliers, consume limited storage, and offer an economical alternative to conventional implementations for decimation and interpolation.

Abstract

A class of digital linear phase finite impulse response (FIR) filters for decimation (sampling rate decrease) and interpolation (sampling rate increase) are presented. They require no multipliers and use limited storage making them an economical alternative to conventional implementations for certain applications. A digital filter in this class consists of cascaded ideal integrator stages operating at a high sampling rate and an equal number of comb stages operating at a low sampling rate. Together, a single integrator-comb pair produces a uniform FIR. The number of cascaded integrator-comb pairs is chosen to meet design requirements for aliasing or imaging error. Design procedures and examples are given for both decimation and interpolation filters with the emphasis on frequency response and register width.