Quick on-chip self- and mutual-inductance screen

Abstract

In this paper, based on simulations of top-level interconnects and CMOS devices of industrial 0.18 /spl mu/m technology, the rules to screen out those inductive interconnects requiring more accurate RLC considerations, and the victim wires potentially having significant inductive noises are developed. The presented criteria constitute a tighter self-inductance screening rule than those found in previously published work. The 2/spl times/mutual inductance screening rule is presented and verified. The differences in on-chip inductance consideration, the significant frequency of a trapezoidal pulse, and the circuit modeling of on-chip inductance are also discussed.