A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range

Abstract

We propose a CMOS image sensor operating at ultra-low voltage (ULV) in a 65-nm low-power (LP) CMOS logic process for ultra-low-power SoC integration. Energy of 17-pJ/frame.pixel and 4×4-µm pixel size with 57-% fill factor are achieved at 0.5 V with digital pixel sensor (DPS) and time-based readout while reaching 40-dB dynamic range (DR) despite high leakage currents and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> variability, thanks to delta-reset sampling (DRS) as well as gating and adaptive body biasing (ABB) of the 2-transistor (2-T) in-pixel comparator.