IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1993 · 14 citations · 9 references
Natural SciencesComputer ScienceElectrical EngineeringAlgorithmsDesign OptimizationOptimizationCombinatorial OptimizationLayout OptimizationMetaheuristic OptimizationOptimization-based DesignGreedy HeuristicsLayout Optimization AlgorithmsPolynomial Time ComplexityPolynomial-time AlgorithmsSimulated Annealing Layout OptimizationSystem Layout OptimizationWire SizingWirelength Optimization
The problem of flipping modules about their horizontal and/or vertical axes so as to minimize the estimated total wire length is considered. Polynomial time algorithms are proposed for some classes of module layouts. Further, it is shown that a simple greedy heuristic often outperforms the neural network and simulated annealing heuristics proposed earlier for this problem.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
9
Bristle Blocks: A Silicon Compiler
Dave Johannsen · CalTechCONF (Cal Tech) · 1979 · 130 citations
MacPitts: An Approach to Silicon Compilation
Bridge: a versatile behavioral synthesis system
Chia-Jeng Tseng, Ruey-Sing Wei, S.G. Rothweiler et al. · Design Automation Conference · 1988 · 71 citations