An FFT Core for DVB‐T/DVB‐H Receivers

Abstract

This paper presents the design and implementation of a 2K/4K/8K multiple mode FFT core for DVB‐T/DVB‐H receivers. The proposed core is based on a pipeline radix‐2 2 SDF architecture. The necessary changes in the radix‐2 2 SDF architecture to achieve an efficient FFT implementation are detailed. Quantization effects and timing design parameters are analyzed for DVB‐T/DVB‐H. Area and power results are provided for the proposed core.