A hybrid analog and digital VLSI neural network for intracardiac morphology classification

Abstract

Current Implantable Cardioverter Defibrillators (ICD's) use timing based decision trees for cardiac arrhythmia classification. Timing alone does not distinguish all rhythms for all patients. Hence, more computationally intensive morphology analysis is required for complete diagnosis. An analog VLSI neural network has been designed and tested to perform cardiac morphology classification tasks. Analog techniques were chosen to meet the strict power and area requirements of the implantable system while incurring the design difficulties of noise, drift and offsets inherent in analog approaches. The robustness of the neural network architecture however, to a large extent, overcomes these inherent shortcomings of the analog approach. The network is a 10:6:3 multilayer perceptron with on chip digital weight storage. The chip also includes a bucket brigade input to feed the Intracardiac Electrogram (ICEG) to the network and a Winner Take All circuit for converting classifications to a binary representation. The training system trained the network in loop and included a commercial implantable defibrillator in the signal processing path. The system has successfully distinguished two arrhythmia classes on a morphological basis for seven different patients with an average of 95% true positive and 97% true negative detections for the dangerous rhythm. The chip was implemented in 1.2 /spl mu/m CMOS and consumes less than 200 nW maximum average power from a 3 V supply in an area of 2.2/spl times/2.2 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>