A CMOS Chip With Active Pixel Array and Specific Test Features for Subretinal Implantation

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents a CMOS imager chip that is aimed at subretinal implantation for partially restoring human vision. It has low supply voltage (<formula formulatype="inline"><tex Notation="TeX">$\pm$</tex></formula> 2 V) and all DC free terminals for long life wired operation. Stimulation voltage is increased to approximately 4 <formula formulatype="inline"><tex Notation="TeX">${\rm V}_{\rm pp}$</tex></formula> by low voltage drop design. 40 x 40 pixel cells including light sensors, amplifiers, control logic and electrode drivers are addressed sequentially to improve power consumption and spatial resolution of perception. Pad count is limited to 6, which requires a specific test procedure. The 3 x 3 mm<formula formulatype="inline"><tex Notation="TeX">$^{2}$</tex> </formula> design is fabricated in a 0.35 <formula formulatype="inline"><tex Notation="TeX">$\mu{\hbox{m}}$</tex></formula> CMOS technology optimized for optical performance. </para>