A 2-kbit superconducting memory chip

Abstract

A 2-kb nondestructive readout memory chip has been built using an Nb/AlO/sub x//Nb Josephson-junction process with a 2.5- mu m design rule. A bitmap of 56% functional cells among 1.5 K tested cells, a read access time of 200 ps, an average cycle time of 500 ps without the decoder, and a power dissipation of 1.6 mW including peripheral circuits have been obtained. The decoding time is estimated to be 540 ps. The circuits in this 5-mm by 5-mm, 24-pin chip includes 2 K memory cells, 6-b decoder and drivers, serial-to-parallel and parallel-to-serial converters, and circuits for design of testability or timing measurements. More than 14000 junctions are used on the chip.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>