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Non-uniform ACC Circuit Lower Bounds
124
Citations
49
References
2011
Year
Unknown Venue
Circuit ComplexityTheory Of ComputingComputational Complexity TheoryEngineeringComputability TheoryAlgebraic ComplexityLower BoundComputer EngineeringMathematical FoundationsComputational ComplexityTime ComplexityCircuit FamiliesComputer ScienceConstant DepthApproximation TheoryCircuit AnalysisClass Acc
The class ACC consists of circuit families with constant depth over unbounded fan-in AND, OR, NOT, and MODm gates, where m >; 1 is an arbitrary constant. We prove: 1. NTIME[2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ] does not have non-uniform ACC circuits of polynomial size. The size lower bound can be strengthened to quasi-polynomials and other less natural functions. 2. E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NP</sup> , the class of languages recognized in 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O(n)</sup> time with an NP oracle, doesn't have non-uniform ACC circuits of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">no(1)</sup> size. The lower bound gives a size-depth tradeoff: for every d, m there is a δ >; 0 such that E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NP</sup> doesn't have s depth-d ACC circuits of size 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nδ</sup> with MOD <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> gates. Previously, it was not known whether EXP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NP</sup> had depth-3 polynomial size circuits made out of only MOD <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> gates. The high-level strategy is to design faster algorithms for the circuit satisfiability problem over ACC circuits, then prove that such algorithms can be applied to obtain the above lower bounds.
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