Power synchronization control for capacitor minimization in Solid State Transformers (SST)

Abstract

The Solid State Transformer (SST) has been researched and designed to interface with the distribution system. The SST consists of a multilevel AC/DC rectifier stage, a bidirectional DC/DC converter stage and a DC/AC inverter stage. However, in all of the previous designs, large capacitors are required to limit the DC bus voltage ripple within the allowable range and stabilize the multistage system. The large capacitors, especially at high voltage level, result in a large size and volume, as well as significant component cost. This paper proposes a feed-forward power ripple control and an inverter power synchronization control method to reduce the required DC filter capacitance and the 120Hz voltage ripple for high voltage and low voltage DC buses. The switching model simulations illustrate the DC bus capacitance can be greatly reduced comparing to the conventional designed value and meet the same voltage ripple requirements. The SST prototype experiments also validate the proposed power synchronization controller.