IEEE Journal of Solid-State Circuits · 1996 · 20 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignSwitch-mode Power SuppliesAnalog MultipliersHigh-voltage Power SupplyLow-power MultipliersLow-voltage Cmos DesignMultiplier DesignMultipliersNonlinearityVoltage
This paper presents a switched-current multiplier, designed for 3.3 V supply voltage, performing 0.625 M multiplications per second with a maximum nonlinearity of 0.94%. The die area is 100/spl times/75 /spl mu/m/sup 2/ in a 2.4 /spl mu/m n-well CMOS process.
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