A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC

Abstract

This paper describes a circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for portable audio-visual equipment. Two new circuit techniques, termed pipelined capacitive interpolation and error averaging circuits with capacitor networks, are developed. As a result, very low power dissipation of 30 mW at a low power-supply voltage of 2.5 V is attained at the conversion frequency of 20 MHz. Also, a good DNL of less than +or-0.5 LSB and an acceptable signal-to-noise and distortion ratio of 55 dB are obtained for the input frequencies of 1 kHz and 1 MHz, respectively. The ADC is fabricated in 0.8- mu m CMOS technology and occupies an area of 2.6*2.5 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>