A highly-parallel VLSI architecture for a list sphere detector

Abstract

Finding the nearest point in a lattice is an NP-hard problem for which we desire a simplified architecture. Furthermore, output of confidence measures or soft information is desirable for decoding/detection problems, yet generating such information further complicates the task. This paper presents an efficient and highly parallelisable architecture for a list sphere detector that is particularly suited to ASIC implementation. Various degrees of parallelism are explored and compared. This architecture finds application in multiuser and MIMO detectors, providing soft estimates of the transmitted symbols.