A 32-GS/s 6-Bit Double-Sampling DAC in InP HBT Technology

Abstract

This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for a coherent optical transceiver based on digital signal processing (DSP). To achieve a high sampling rate, a novel double-sampling technique was devised. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> of 175 GHz and a peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 260 GHz. Measured DNL and INL were within +0.49/-0.17 LSB and +0.97/-0.06 LSB, respectively. Measured SFDR was 45.0 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which is the limit of our measurement setup. Ramp-wave output at a sampling rate of 32 GS/s was obtained. Total power consumption was 1.4 W with a supply voltage of -4.0 V. To our knowledge, this is the first 6-bit DAC that can operate at a sampling rate of over 30 GS/s.