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High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs
496
Citations
14
References
2009
Year
Low-power ElectronicsElectrical EngineeringEngineeringRf SemiconductorRadio FrequencyHigh-frequency DeviceAntennaBeyond CmosPower ElectronicsUhf RfidsMicroelectronicsTransistor SizingRf SubsystemPeak PceElectromagnetic Compatibility
The authors developed a high‑efficiency CMOS rectifier for UHF RFID applications. The rectifier employs a cross‑coupled bridge driven by a differential RF input and a differential‑drive active‑gate bias that lowers ON‑resistance and reverse leakage, enabling high power‑conversion efficiency; it was fabricated in 0.18 µm CMOS, tested across frequencies, loads, and transistor sizes, and extended to a multi‑stage design for higher DC output. The device achieved a peak 67.5 % power‑conversion efficiency at 953 MHz, –12.5 dBm input and 10 kΩ load—twice the best reported value—and showed that efficiency rises with lower frequency, higher load resistance, and an optimal transistor size.
A high-efficiency CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive active gate bias mechanism simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency (PCE), especially under small RF input power conditions. A test circuit of the proposed differential-drive rectifier was fabricated with 0.18 mu m CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on the input RF signal frequency, output loading conditions and transistor sizing was also evaluated. At the single-stage configuration, 67.5% of PCE was achieved under conditions of 953 MHz, - 12.5 dBm RF input and 10 KOmega output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance. In addition, experimental results show the existence of an optimum transistor size in accordance with the output loading conditions. The multi-stage configuration for larger output DC voltage is also presented.
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