Concepedia

Abstract

This paper reports on a field-programmable analog array (FPAA) for high-frequency continuous-time analog filters. A rapid-prototyping hardware is presented, which implements a unique hexagonal lattice topology of 55 tunable G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> cells for reconfigurable instantiation of G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -C filters in a 0.13 mum CMOS technology. The typical power dissipation is 70 mW at a 1.2 V supply. The chip structure allows intuitive mapping of G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -C filter schematics with up to seven independent nodes, immediate download to the hardware, and evaluation on the working prototype. Implementations of first- and second-order low-pass and sixth-order bandpass filters are presented and show the feasibility of the array for frequencies up to the order of one hundred MHz.

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