High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor

Abstract

A progressive 1/1.8-inch 1920times1440 CMOS image sensor with a column-inline dual CDS architecture uses a 0.18mum CMOS process. This sensor implements digital double sampling with analog CDS on a column parallel ADC. Random noise is 5.2e- <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> and the DR is 68dB at 180frames/s(6.0Gb/s). FPN is <0.5e- <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> without the correction circuit