FPGA implementation of a spiking neural network for pattern matching

Abstract

A field programmable gate array (FPGA) implementation of a hardware spiking neural network is presented. The system is able to realize different signal processing tasks using the synchronization of oscillatory leaky integrate and fire neurons. The use of a bit slice architecture and short, local interconnections make it adaptable to projects of various scales. The system is also designed to efficiently process groups of synchronized neurons. A fully connected network of 648 neurons and 419904 synapses is implemented on a stand-alone Xilinx XC5VSX50T FPGA, processing up to 6M spikes/s. We describe the resource usage for the whole system as well as for each functional block, and illustrate the functioning of the circuit on a simple image recognition task.