Load-sensitive flip-flop characterizations

Abstract

Different flip-flop designs vary in the number and complexity of logic stages they contain, and hence have different inherent parasitic delays and output drive strengths. We examine the effect of electrical load on flip-flop delay and energy consumption and show that the relative ranking of optimized flip-flop structures varies widely with both electrical effort and absolute load. We also show that some structures benefit substantially from the addition of appropriate output buffering.