Hybrid DPWM with Digital Delay-Locked Loop

TLDR

The paper introduces a fully synthesizable hybrid digital pulse width modulator (DPWM). The DPWM employs a digital delay‑locked loop around a delay line with discretely programmable delay cells to maintain constant‑frequency operation across process and temperature variations, supports trailing‑edge, leading‑edge, and triangular modulation, offers two outputs with programmable dead‑times for synchronous DC‑DC converters, and is suitable for FPGA or custom chip implementation. Experimental results demonstrate a 780 kHz, 10‑bit FPGA implementation.

Abstract

This paper introduces a fully synthesizable hybrid digital pulse width modulator (DPWM). The DPWM includes a digital delay locked loop around a delay-line with discretely programmable delay cells to achieve constant-frequency clocked operation with the best possible resolution over a range of process or temperature variations. The DPWM module can implement trailing-edge, leading-edge or triangular modulation. It includes two outputs with programmable dead-times, suitable for DC-DC converters with synchronous rectifiers. The DPWM module is well suited for FPGA or custom chip implementation. Experimental results are shown for a 780 KHz, 10-bit FPGA realization