Systematic architecture exploration for implementing interference suppression techniques in wireless receivers

Abstract

Future wireless systems are required to provide higher data rates, improved spectral efficiency and greater capacity. This can be achieved at the cost of increased signal processing complexity. The successful implementation of advanced algorithms and dedicated hardware architectures to tackle the demanding signal processing tasks calls for an integrated development process. It must effectively exploit the many interrelations between the different levels of the design hierarchy and efficiently bridge the gap between system concepts and their VLSI circuit realization. This paper presents the algorithm and architecture level design of interference suppression techniques for advanced wireless receivers based on the use of multiple antenna elements in combination with appropriate signal combining. A systematic approach to architecture exploration is demonstrated which leads to efficient implementations in terms of both power consumption and silicon area.