On-chip ΔI noise in the power distribution networks of high speed CMOS integrated circuits

Abstract

On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped RLC model. The peak value of the simultaneous switching noise voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak simultaneous switching noise voltage on the circuit behavior.