Optimization of LDMOS array design for SOA and hot carrier lifetime

Abstract

Optimization of LDMOS devices to meet safe operating area (SOA) and hot carrier lifetime targets is a current challenge for process development. This work focuses on novel results in the use of layout techniques and cell design to improve both SOA and hot carrier reliability of LDMOS arrays. Specific improvements to cell based array layouts that increase SOA and hot carrier lifetime for fixed transistor architecture are reported.