IEEE Transactions on Circuits & Systems II Express Briefs · 2011 · 26 citations · 5 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsClock ManagementCmos Circuit DesignDigital Integrated CircuitsHigh-frequency Semiconductor DevicesMixed-signal Integrated Circuit DesignRadio-frequency Integrated CircuitsClock Data RecoveryClock Generation CircuitsClock RecoveryPower ConsumptionVoltage-controlled Oscillator Design
A 1-16-Gb/s wide-range clock and data recovery (CDR) circuit is presented by using the proposed bidirectional frequency detector. This CDR circuit is fabricated in 0.13-μm CMOS technology, and its active area is 0.134 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> without a loop filter. The power consumption of this CDR circuit is 160 mW for a supply of 1.5 V. A modified interpolation voltage-controlled oscillator is presented, which covers from 4.9 to 10.2 GHz. A quadrature divider is used to generate accurate quadrature clocks.
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