High Resolution FPGA DPWM Based on Variable Clock Phase Shifting

Abstract

This letter proposes a very high resolution digital pulsewidth modulator (DPWM) architecture that takes advantage of a field-programmable gate array (FPGA) advanced clock management capability - the fine phase shifting of the clock. This feature is available in almost every FPGA nowadays, thus allowing very small and programmable delays between the input and output clocks. An original use of this fine phase shifting pushes the limits of DPWM resolution. The experimental results show a time resolution of 19.5 ps in a Virtex-5 FPGA.