A 75.5-to-120.5-GHz, high-gain CMOS low-noise amplifier

Abstract

In this paper, a high-gain and wideband low-noise amplifier using 65-nm CMOS process is proposed. A four-stage cascode configuration is adopted to achieve the high gain and wideband performance. With 24-mA dc current and 2-V supply voltage, the LNA not only provides gain higher than 20 dB from 75.5 GHz to 120.5 GHz, but also has a measured noise figure between 6 and 8.3 dB from 87 to 100 GHz. The output 1-dB compression power (OP <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</inf> ) is −3 dBm at 110 GHz, and the chip size is 0.55 × 0.45 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .