Area-delay tradeoff in distributed arithmetic based implementation of FIR filters

Abstract

In this paper we present coefficient memory vs number of additions tradeoff in distributed arithmetic based implementation of FIR filters. Such a capability is key to be able to explore a wider search space during system level design. We present two techniques based an multiple memory banks and multirate architectures to achieve this tradeoff. These techniques along with 1-bit-at-a-time and 2-bits-at-a-time data access mechanisms enable as many as 16 different data points in the area-delay space. We present analytical expressions to compute coefficient memory size and number of additions for these implementations. We present results for all the 16 DA based implementations of three FIR filters with two values of input data precision. We also present the resultant area-delay curves for these filters.