Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

Abstract

Several techniques to reduce the ground bounce effect in CMOS chips are described. The effective width of the predrive and final driver of a CMOS output buffer is automatically adjusted to compensate for process, voltage, and temperature (PVT) variations. The slew rate of the predrive nodes is controlled by introducing a digitally weighted capacitance. Finally, a compensated active resistance is inserted into both the power and ground leads to further dampen the oscillations. These techniques allow the buffer to behave uniformly over the entire PVT range. Measurements of a 0.5-/spl mu/m CMOS test chip have demonstrated that these new buffers generate 2.5/spl times/ less ground bounce when compared to conventional buffers. An external resistance is required to set a reference current.