FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers

Abstract

A pipelinable bit-serial multiplier using Canonic Signed Digit, or CSD code to represent constant coefficients is introduced. A bit-serial module for a(x/spl plusmn/y)z/sup -1/ type computation is further developed. Optimization over discrete power-of-two coefficient space has been retargeted on this type of multiplier to generate minimized no-zero bit coefficients. This also make it possible to confine the latency to be equivalent to the data wordlength without causing a large delay in partial product sum propagation. A single chip FPGA implementation of a full 16-bit 31-tap Hilbert transformer is used as an example to demonstrate the application of the multiplier module with the special consideration of FPGA architectures. It is shown that FPGA architecture is an ideal vehicle for thus optimized bit-serial processing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>