Bilinear switched-capacitor ladder filters

Abstract

Design techniques are described for parasitic-insensitive switched-capacitor ladder filters, whose response is related to that of continuous-time filters by the bilinear s-to-z transformation. A modification of the process, which reduces the necessary number of amplifiers but complicates the switching sequence, is also discussed. The proposed schemes are completely free of the approximation errors inherent in the presently used LDI-based design techniques. The resulting circuits have low sensitivities both to element-value variations and to parasitic capacitances.