Electrical modeling and characterization of 3-D vias

Abstract

Electrical characterization of the resistance, capacitance, and inductance of inter-plane 3-D vias is presented in this paper. Both capacitive and inductive coupling between multiple 3-D vias is described as a function of the separation distance and plane location. The effects of placing a third shield via between two signal vias is investigated as a means to limit the capacitive coupling. The location of the return path is examined to determine the best placement of a 3-D via to reduce the overall loop inductance. Based on the extracted resistance, capacitance, and inductance, the L/R time constant is shown to be much larger than the RC time constant, demonstrating that the 3-D via structure investigated in this paper is inductively limited rather than capacitively limited.