A 0.18μm CMOS equalizer with an improved multiplier for 4-PAM/20Gbps throughput over 20 inch FR-4 backplane channels

Abstract

In this paper, we present a 20 Gbps throughput PAM-4 analog feed forward equalizer with a newly proposed multiplier cell. The conventional Gilbert-cell multiplier is modified to achieve enough voltage headroom for 0.18/spl mu/m standard CMOS process while maintaining high-speed characteristics. Pulse amplitude modulation (PAM)-4 is adopted to increase the overall data throughput over bandwidth limited channel. For the tap delay line implementation, a passive L-C ladder topology is used, which enables fractional symbol tap spacing while maintaining the bandwidth required for 20 Gbps PAM-4 signal. The overall architecture is implemented using 0.18 /spl mu/m, standard CMOS process with 1.8V supply voltage. The 20 Gbps PAM-4 signal is received through the backplane channel, and the signal impairment is successfully compensated through the fabricated FFE.