Codevelopment of the TMS320C6X VelociTI architecture and compiler

Abstract

Continuing dramatic improvements in semiconductor manufacturing processes are enabling radical new signal processing architectures at the chip level. The development of these new architectures must be coupled with clearly defined target applications, a thorough analysis of applicable signal processing algorithms, and significant advancements in code-generation technology. The TMS320C6x development program involved the codevelopment of the VelociTI architecture, a new code-generation capability, and a large set of representative benchmarks.