High throughput hardware architecture for (1440,1344) low-density parity-check code utilizing quasi-cyclic structure

Abstract

High throughput architecture of an encoder and a decoder for a quasi-cyclic low-density parity-check (LDPC) code is proposed. A new systematic encoding method is carried out by polynomial manipulation. The proposed decoder architecture, where the check-node process is split into two processes so that the memory access becomes column-wise, enables overlapped message-passing for any parity-check matrix. The hardware architecture for the check-node processes utilizing a quasi-cyclic structure does not require complex multiplexers. Hardware employing the proposed architecture for a (1440,1344) LDPC code designed for high throughput millimeter wave application is evaluated using 65 nm CMOS technology. The gate count of the encoder for 3 Gbps and 6 Gbps throughput is 2.5 k and 3.1 k, respectively, and the gate count of the decoder for 8 iterations is 304 k and 409 k, respectively. A bit-error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−6</sup> is obtained at E <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</inf> /N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</inf> of 5.9 dB, and the estimated power consumption of the decoder is 58 mW for 3 Gbps and 86 mW for 6 Gbps.