Rapid design of a single chip adaptive beamformer

Abstract

This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 gigaflops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realise the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.