Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

TLDR

Silicon optical technology is still emerging, but rapid progress in on‑chip optical interconnects has made chip‑to‑chip communication a near‑term focus. The paper investigates integrating CMOS‑compatible optical technology into on‑chip cache‑coherent buses for future CMPs. The authors design a hierarchical opto‑electrical bus that embeds CMOS‑compatible optical links into cache‑coherent buses, leveraging optical benefits while respecting projected limitations. Evaluation shows that, compared to an aggressive all‑electrical bus of similar power and area, the opto‑electrical bus delivers significant performance gains that depend on application bandwidth demand and the number of wavelengths per waveguide, and identifies key areas for future work.

Abstract

Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the development of on-chip optical interconnects. In this paper, we investigate the integration of CMOS-compatible optical technology to on-chip cache-coherent buses in future CMPs. While not exhaustive, our investigation yields a hierarchical opto-electrical system that exploits the advantages of optical technology while abiding by projected limitations. Our evaluation shows that, for the applications considered, compared to an aggressive all-electrical bus of similar power and area, significant performance improvements can be achieved using an opto-electrical bus. This performance improvement is largely dependent on the application's bandwidth demand and on the number of implemented wavelengths per optical waveguide. We also present a number of critical areas for future work that we discover in the course of our research