A simple via duplication tool for yield enhancement

Abstract

Defect limited product yields are known to have a significant contribution from resistive or open vias between metal interconnect layers. A simple tool for via duplication is presented with application results. The tool automates the addition of redundant vias to existing customer product layouts where permitted by the design rules. Significant yield benefits are obtained when the technique is applied to a real product as part of a Design for Manufacturability (DfM) exercise. The potential for improved process robustness and enhanced fault tolerance is also demonstrated. Implications for yield modeling including critical areas and the relation of random defects to gross defects are discussed.