Concepedia

TLDR

Dynamic Partial Reconfiguration (DPR) offers flexible, efficient system design, yet current design flows are low‑level, complex, or lack automatic synthesis support. The paper presents a SystemC‑based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. The approach handles reconfiguration at the application level, enabling early exploration and analysis of DPR effects. The flow enables rapid implementation of reconfigurable systems, as demonstrated on an educational example.

Abstract

Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this paper, we present a SystemC based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. Our approach addresses reconfiguration already on application level enabling early exploration and analysis of the effects of DPR. Moreover it also allows quick implementation of such systems using our automatic synthesis flow. We demonstrate our approach using an educational example.

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