Design of a Dual W- and D-Band PLL

Abstract

This paper describes the design considerations and performance of the highest frequency phase-locked loop (PLL) reported to date. The PLL was fabricated in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox{m}}$</tex> </formula> SiGe BiCMOS process and integrates on a single die: a fundamental-frequency 86–92 GHz Colpitts voltage-controlled oscillator (VCO), a differential push-push 160-GHz Colpitts VCO with two differential outputs at 80 GHz, a programmable divider chain, the charge pump, and all loop filter components. It achieves the lowest W- and D-band phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$-\hbox{93~dBc}/{\hbox{Hz}}$</tex></formula> at 90 GHz and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{87.5~dBc}/{\hbox{Hz}}$</tex> </formula> at 163 GHz, both measured at a 100 kHz offset, and demonstrates an extended locking range of 80–100 GHz at the fundamental frequency, and 160–169 GHz at the second harmonic output of the push-push VCO. The single-ended PLL output power is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{3~dBm}$</tex> </formula> at 90 GHz and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{25~dBm}$</tex> </formula> at 164 GHz. The chip consumes 1.25 W from 1.8 V, 2.5 V, and 3.3 V supplies and occupies 1.1 mm x 1.7 mm , including pads.