A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces

Abstract

A 6 b 10-tap digital FIR filter has a self-timed datapath, clocked interfaces, and variable latency. The architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. The 0.45 mm/sup 2/ circuit, in 0.18 μm CMOS technology, is operational from 1.2 V to 2.1 V power supply, and has 80 mW dissipation at 300 MSample/s and 4 cycles of latency, and 500 mW at 1.3 GSample/s and 7 cycles of latency.