Electrical Modeling of Lithographic Imperfections

Abstract

Lithographic wavelength of 193 nm has been used for past few generations of patterning and is likely to remain in use for next few technology generations (at least till 28 nm technology half-node) as well. This deep sub-wavelength patterning has resulted in wafer shapes not resembling drawn rectilinear shapes. The resulting non-rectangular devices and wires are not handled by current generation modeling and analyses methods. In this paper, we present a survey of electrical modeling methods for such lithographic imperfections especially on transistor layers. We also discuss use contexts of such models as well as briefly present electrical implications of the likely future patterning candidate, namely double patterning.