A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN

Abstract

A clock-skew tolerant 8-bit 16x time-interleaved (TI) SAR ADC is presented that meets WiGig standard requirements with only background offset and gain calibrations. By using a “correct-by-construction”, timing-calibration-free global bottom-plate sampling scheme, the ADC achieves a sampling rate of 2.64GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40nm LP CMOS design dissipates 39mW from 1.2V. The TI-SAR ADC characterized with an integrated receiver front-end achieves −21.44dB EVM at sensitivity with an OFDM/ QAM16 signal.