Publication | Closed Access
Fully static 16Kb bulk CMOS RAM
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1980
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Unknown Venue
Hardware SecurityElectrical EngineeringMemory ArchitectureEngineeringVlsi DesignComputer EngineeringComputer ArchitectureBulk Cmos RamSemiconductor MemorySix-transistor CellParallel ComputingMicroelectronicsStatic 16KbMulti-channel Memory Architecture
A coplanar Si-gate CMOS process used in the design of a fully static 16Kb bulk CMOS RAM with a six-transistor cell will be covered. RAM offers a typical 95ns access time with 200mW power dissipation and 1μW standby power.