Low-phase-noise wide-frequency-range ring-VCO-based scalable PLL with subharmonic injection locking in 0.18 µm CMOS

Abstract

A low-phase-noise ring-VCO-based PLL (frequency tuning range: 0.65–1.6 GHz ) with subharmonic injection locking was realized (PLL area: 0.1mm2) by adopting 0.18 µm CMOS technology and combining pMOS resistive loads with a circuit for shifting bias levels; this makes the rail-to-rail range of voltages usable as control voltages. For a 90-MHz input reference signal, without injection locking, the 0.2-MHz-offset phase noise was −108 dBc/Hz (PLL output frequency: 1.44 GHz = 16 × 90 MHz); with injection locking, the noise was −122 dBc/Hz (spurious level: −35 dBc; power consumption from a 1.8V power supply: 39 mW).