Two's-complement fast serial-parallel multiplier

Abstract

A fast serial-parallel multiplier based on the Baugh-Wooley algorithm is proposed. It is shown that sign extension of the sum or carry bit, produced during the addition of the bit product rows, can be avoided, and a more efficient multiplier can be obtained. The multiplier is compared with one proposed recently in terms of speed and hardware, and is shown to be faster, to need less hardware and to have a lower area*time2 complexity.