Design and Analysis of Novel Linearization Technique of Cascode Cell in a 60-GHz CMOS Demodulator

Abstract

CMOS cascode device pairs are widely used in many applications. To improve the linearity of the cascode amplification cell while maintaining reasonable gain, a new technique, called splitting cascode, is proposed in this paper. The original cascode is split into two sub-cells to investigate the linearity behavior. With this technique, the third-order intermodulation (IM3) distortion of a cascode amplifier can be greatly improved by 29 dB at 56 GHz. Due to its simple structure, yet significant linearity improvement to the traditional cascode cell, this novel technique can be used in almost every circuit where the cascode cell is used to amplify a signal. To measure the effect of reduction of the IM3 distortion after linearization, two sub-harmonically pumped down conversion mixers are applied to convert the signal to lower frequency. If the mixers are driven by two local oscillator signals with 45 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> phase difference, the whole circuit forms a 60-GHz demodulator. The measurement results show an improvement in the IM3 distortion level of more than 20 dB from 54 to 66 GHz. The measurement results show the proposed method can bring linearity improvement in wide input power range. To the authors' knowledge, this is the first linearization method realized in CMOS technology with an operation frequency around 60 GHz.