PipeRench: a reconfigurable architecture and compiler

TLDR

Embedded systems now face diverse workloads that general‑purpose processors cannot efficiently handle, and custom hardware is rarely feasible; reconfigurable computing offers a flexible yet efficient alternative. The authors propose PipeRench, a new reconfigurable computing architecture with an associated compiler. PipeRench integrates with conventional processors to meet diverse computing needs without custom hardware, addressing FPGA issues such as logic granularity, configuration time, forward compatibility, hard constraints, and compilation time.

Abstract

With the proliferation of highly specialized embedded computer systems has come a diversification of workloads for computing devices. General-purpose processors are struggling to efficiently meet these applications' disparate needs, and custom hardware is rarely feasible. According to the authors, reconfigurable computing, which combines the flexibility of general-purpose processors with the efficiency of custom hardware, can provide the alternative. PipeRench and its associated compiler comprise the authors' new architecture for reconfigurable computing. Combined with a traditional digital signal processor, microcontroller or general-purpose processor, PipeRench can support a system's various computing needs without requiring custom hardware. The authors describe the PipeRench architecture and how it solves some of the pre-existing problems with FPGA architectures, such as logic granularity, configuration time, forward compatibility, hard constraints and compilation time.