An Extended Topology of Parallel-Circuit Class-E Power Amplifier Using Transmission-Line Compensation

Abstract

This paper presents a parallel-circuit Class-E amplifier that maintains it operating characteristics even when the output capacitance of the transistor is greater than the optimum shunt capacitance. The finite dc feed inductor in the parallel circuit topology is replaced by a transmission-line compensation circuit to eliminate the limitations on the operating frequency imposed by the output capacitance. Theoretical formulas for the circuit elements of the proposed network are derived in detail, and the analysis is validated by simulation and measurement. The measured maximum output power of 40.1 dBm, drain efficiency of 77.5%, and power-added efficiency of 70.8% were obtained at 2.8 GHz with a 29.4-dBm input power. These measurements show a similar or better level of efficiency and output power that is reported for other amplifiers at lower frequencies using the same transistor.